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Microwind 3

The MICROWIND software allows the designer to simulate and design an integrated circuit at physical description level. 

Microwind3 unifies schematic entry, pattern based simulator, SPICE extraction of schematic, Verilog extractor, layout compilation, on layout mix-signal circuit simulation, cross sectional & 3D viewer, netlist extraction, BSIM4 tutorial on MOS devices and sign-off correlation to deliver unmatched design performance and designer productivity. The package contains a library of common logic and analog ICs to view and simulate.

Microwind3 includes all the commands for a mask editor as well as, you can gain access to Circuit Simulation by pressing just one single key. The electric extraction of your circuit is automatically performed and the analog simulator produces voltage and current curves immediately.

The tool features full editing facilities, various views, and an on-line analog simulator. 

The MICROWIND software has following segments in it:

Schematic Editor and Simulator

Precision CMOS Layout tool upto 22 nanometers

Touch the Deep-Sub Micron Technology

 Mixed Signal Simulation and Analysis

MOS characteristic viewer and trainer

 Non Volatile Flaoting Gate Memory Simulators

DSCH

The DSCH program is a logic editor and simulator. DSCH is used to validate the architecture of the logic circuit before the microelectronics design is started. DSCH provides a user-friendly environment for hierarchical logic design, and fast simulation with delay analysis, which allows the design and validation of complex logic structures.

DSCH also features the symbols, models and assembly support for 8051 and 16F84 controllers. Designers can create logic circuits for interfacing with these controllers and verify software programs using DSCH.

• User-friendly environment for rapid design of logic circuits.
• Handles both conventional pattern-based logic simulation and intuitive on-screen mouse-driven simulation.
• Supports hierarchical logic design
• Built-in extractor which generates a SPICE netlist from the schematic diagram (Compatible with PSPICE™ and WinSpice™).
• Current and power consumption analysis.
• Generates a VERILOG description of the schematic for layout editor
• Immediate access to symbol properties (Delay, fanout)
• Models and assembly support for 8051 and PIC 18f84
• Sub-micron, deep-submicron, nanoscale technology support.
• Supported by huge symbol library.

nanoLambda

MICROWIND possess a precision CMOS layout editor, which supports technologies right from 1.2µm till 22 nm with unsurpassed illustration capabilities. With its enhanced editing commands and layout control your development times would be shorter than you ever imagined.

• Huge technology support till 22 nanometers.
• Sub-micron, deep-submicron, ultra deep-submicron, nanoscale technology support.
• Design-error-free cell library (Contacts, vias, MOS devices, etc.).
• Advanced macro generator (Capacitor, MOS transistor, matrix, ROM, pads, inductors, path, etc.)
• Virtual components library (R,L,C, etc) for faster simulation response.
• Incredible translator from logic expression into compact design-error free layout.
• Powerful automatic compiler from Verilog structure circuit into layout.
• Built-in extractor which generates a SPICE netlist from layout.
• Extraction of all MOS width and length.
• Parasitic capacitance, inductance, crosstalk and resistance extracted for all electrical nodes.
• Modular design support with insert mask layout facility.
• Import/Export CIF layout from 3rd party layout tools.
• Supports up to 100,000 elementary boxes.
• Lock & unlock layers to protect some part of the design from any changes.
• Support upto 8 metal layers for DSM technologies.
• Global delay evaluation of circuit with facility to dump RC values.
• Global cross talk analyzer.
• Inversion of diffusions boxes.
• Easy label listing.
• Enhanced mathematical signal description for advance users.
• Zoom in navigator.
• Enhanced memory utilization for faster simulation.
• Silicon atom viewer with 3D support allows students to understand Si atom structure.

VirtuosoFab

You will never teach deep-sub micron technology like before. As VirtuosoFab offers you a facility to analyze and view cross sectional view of silicon layers and 3D view of circuits. With MICROWIND v3.1 a spectacular facility has been added to VirtuosoFab which enables to draw real-time images of the layout and navigate in full-3D on the surface or inside the IC. This command is based on OpenGL and offers outstanding picture quality. The user can modify the viewing position in X,Y,Z and play with light sources to create illustrative views of the layout.

• 3D fabrication process simulator with cross sectional viewer.
• Step-by-step 3-D visualization of fabrication for any portion of layout.
• See how the contacts and metallizations are created.
• See the self-aligned diffusion after the polysilicon gate is fabricated.
• Check planes of VDD, VSS, and others signals.
• See how the contacts and metallizations are created.
• See the self-aligned diffusion after the polysilicon gate is fabricated.
• Check planes of VDD, VSS, and others signals.
• Check the oxide structure, the low dielectric (Low K) and high K (SiO2) Sandwich, and passivation.
• User can check the gate oxide and the MOS lateral drain diffusion structure.
• Advanced 3D layout view with GEL technology.
• 2D cross sectional viewer with strain technology support.

PROThumb

No SPICE or external simulator is needed for verification of CMOS circuits. Microwind program has in built analog like simulator which supports MOS Level 1, Level 3 or BSIM4 model. With features like fast time-domain, voltage and current estimation, very intuitive post processing, frequency estimation, delay estimation, makes PROthumb a time saver. Even power estimation of circuit simulation can be checked on-screen.

• Built-in SPICE-like analog simulator.
• Features fast time-domain, voltage and current estimation, with very intuitive post processing: frequency estimation, delay estimation. (No external SPICE/ analog Simulator required).
• Supports level1, level3 and BSIM4 models for all technologies from 1.2µm till 22 nm.
• MOS characteristic viewer with access to parameters of main model.
• Ability to label nodes allows intuitive control of the simulation (Supply, clock, pulse, PWL, sinus, maths).
• Time-domain voltage and current waveforms available at the press of one single button.
• DC/AC characteristics, signal frequency vs. time, eye diagrams. Min/Typ/Max analog simulation.
• Convenient Monte-carlo simulation.
• Powerful Fast-Fourier Transform to support radio-frequency circuit simulation.
• Eye diagram view for signal output.
• On screen power estimation.
• Sophisticated parametric simulation to investigate the effect of several key parameters on the circuit performances: R,L,C, temperature, supply voltage, etc.
• Huge device simulation model library.
• Inbuilt interconnect analyzer to compute field between ground planes and conductor.
• Enhanced memory utilization for faster simulation.
• Onscreen storage of waveforms for result hold-on.
• Forward & backward buttons to move in simulation results.

PROTutor

A valuable screen to understand the MOS characteristics, with a user interface that designers will like. Change the model parameters and see their effects on Id/Vd, Id/Vg Id(log)/Vg, threshold vs. length. You can also fit the simulations with measurements we made in test-chips fabricated in 0.35, 0.25 and 0.18µm. In the manual, a tutorial on MOS models is given, with details on all parameters. MICROWIND supports MOS models 1, 3 and BSIM4.

• Change the model parameters and see their effects on Id/Vd, Id/Vg, Id(log)/Vg, threshold vs Length.
• You can also fit the simulations with measurements we made in test-chips fabricated in 0.35, 0.25 and 0.18 µm.
• Full length tutorial on MOS models is provided in manual, with details on all parameters.
• Supports level1, level3 and BSIM4 MOS models.
• Documentation includes several aspects of MOS modeling.

MEMsim

The double-gate MOS has been introduced in MICROWIND for the simulation of non-volatile memories such as EPROM, EEPROM and FLASH. The command “UV exposure” erases floating gates and removes all electrons. The programming is performed by a very high voltage supply on the gate (7V in 0.12µm), a 1.2V voltage difference between drain and source. Some electrons are sufficiently accelerated to pass through the gate oxide by hot tunneling effect.

• Simulation of non-volatile memories such as EPROM, EEPROM and FLASH using double-gate MOS
• Erasure of floating gates and removal all electrons.
• Programming can be performed by a very high voltage supply on the gate

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